This invention relates to a thin-film transistor array and, more particularly, to a thin-film transistor array that can be used with advantage for an active matrix liquid crystal display panel.
The following specific analyses have been given on the related art by the inventors in the course of the investigation toward the present invention.
An active matrix type liquid crystal display device, employing a thin-film transistor (xe2x80x98TFTxe2x80x99) as a switching device, is made up of a TFT substrate comprised of a matrix array of TFTs and pixel electrodes and an opposing substrate electrode, arranged opposing the TFT substrate with a liquid crystal material interposed in-between. The opposing substrate electrode includes a light-shielding film (so-called black matrix), a color filter and a common electrode.
FIG. 15 shows a plan view illustrating the structure for one pixel of a typical thin-film transistor array, and FIG. 16 shows a cross-sectional view taken along line G-Gxe2x80x2 of FIG. 15. This structure is referred to as xe2x80x98a first conventional techniquexe2x80x99.
Referring to FIGS. 15 and 16, the structure of the first conventional technique is explained.
The active matrix type liquid crystal display device, employing the TFT as an active device, has a structure in which a gate bus line 111, wired in the horizontal direction from a gate driver, and a drain bus line 112, wired in the vertical direction from a source driver, are connected to a gate electrode 101 and a drain electrode 103 of the TFT device, respectively, and in which a pixel electrode 106 is connected to a source electrode 104 of the TFT device.
When a given gate line 111 goes high, the TFTs connected to this gate bus line 111 are turned on in unison. The pixel electrode 106, connected to this TFT, is charged to a signal voltage applied to the drain bus line 112.
If then the gate bus line 111 goes low, the TFT in the on-state is turned off. However, the pixel electrode 106 keeps on to maintain its charging voltage. This maintained voltage is rewritten by the next signal voltage when the corresponding TFT again goes on.
If the active matrix type liquid crystal display device employing this TFT substrate is to make display of satisfactory quality, it is necessary for the pixel electrode 106 to hold the charging voltage sufficiently until next rewriting.
FIG. 17 shows a cross-sectional view illustrating, step-by-step, the process for manufacturing a typical thin-film transistor array (first conventional technique) shown in FIG. 16. Referring to FIG. 17, the manufacturing method according to the first conventional technique is explained.
A gate electrode 101 formed by a metal film of Cr or Al is patterned on a glass substrate 100, as shown in FIG. 17a. A gate insulating film 114, a channel layer 102 of intrinsic semiconductor amorphous silicon xe2x80x98a-Si(n+)xe2x80x99 and a contact layer 107 of n+ semiconductor amorphous silicon (xe2x80x98a-Si (n+)xe2x80x99 are formed sequentially thereon.
The semiconductor layer is then etched (FIG. 17b) and the gate insulating film 114 of the contact area interconnecting the gate layer and the drain layer are removed by patterning, so that a through-hole, not shown, is formed for interconnecting a metal film forming the gate electrode 101 and a metal film forming the drain electrode 103, source electrode 104 and the drain bus line 112.
Similarly to the drain electrode 101, the drain electrode 103, source electrode 104, drain bus line 112 and the pixel electrode 106 are formed (see FIGS. 17c and 17d) and subsequently a passivation film 115 is formed to complete a TFT array substrate (see FIG. 17e).
Meanwhile, a storage capacitance electrode 108 is formed simultaneously with the gate electrode 101 in the course of the patterning step for forming the gate electrode 101. The storage capacitance electrode 108 faces the pixel electrode 106 via the gate insulating film 114 operating as a storage capacitance insulating film in-between to constitute a storage capacitance.
The opposing substrate side is manufactured by forming a counter-electrode on a glass substrate, not shown.
Finally, orientation films, not shown, are formed on the TFT array substrates and the opposing substrate, by way of orientation processing, after which a sealing pattern is formed and the substrates are then stacked together and fired. Into the fired product is injected a liquid crystal, not shown, and the injection inlet is sealed to complete a liquid crystal panel.
To this liquid crystal panel are added a light polarization plate, a driving circuit and a casing to complete a liquid crystal display device.
FIG. 18 shows a plan view illustrating the structure of one pixel of a representative thin-film transistor array characterized in that the storage capacitance is formed between it and the gate electrode (this structure is referred to as a xe2x80x98second conventional technique). The number of patterning steps and the manufacturing method in this structure are the same as those of the first conventional technique explained in accordance with FIG. 17.
In the TFT of the structure shown in the first conventional technique and in the second conventional technique, the drain bus line 112 and the pixel electrode 106 are both electrically conductive layers each extending over the gate insulating film 114, and are spaced apart from each other by a pre-set distance. However, if residual patterning troubles would occur in any patterning process, shorting is likely to occur between the drain bus line 112 and the pixel electrode 106.
If shorting occurs between the drain bus line 112 and the pixel electrode, charging/discharging of the pixel electrode 106 cannot be controlled by on/off control of the TFT such that the pixels become visible as bright-point defect.
For reducing this shorting, there has been proposed in, for example, JP Patent Kokai JP-A-7-325314 a liquid crystal device in which, as shown in FIG. 19a, by a step difference of the storage capacitance electrode 108, the pixel electrode 106 in the vicinity of the storage capacitance electrode 108 is constricted or retracted, as shown in FIG. 19b, relative to residual a-Si 116, so that the drain bus line 112 and the pixel electrode 106 become difficult to get conductive by the residual a-Si 116. The structure, however, cannot be applied to other than the case of residual a-Si attributable to the step difference of the storage capacitance electrode 108.
There has also been proposed a TFT structure in which the drain bus line 112 and the pixel electrode 106 are laminated via an insulating film interposed in-between for reducing occurrences of shorting. FIG. 20 shows, in a plan view, the structure for one pixel of a TFT array aimed at reducing the shorting between the drain bus line 112 and the pixel electrode 106. FIG. 21 is a cross-sectional view taken along line H-Hxe2x80x2 in FIG. 20 (third conventional technique).
Referring to FIGS. 20 and 21, the structure of the third conventional technique is explained.
In this third conventional technique, the drain bus line 112 is provided on the gate insulating film 114, whilst the pixel electrode 106 is formed on a passivation film 115. The drain bus line 112 and the pixel electrode 106 are separated on the layer basis by the passivation film 115.
FIG. 22 is a process diagram showing, step-by-step, the manufacturing process for a thin-film transistor array (third conventional technique) aimed at reducing shorting between the drain bus line 112 and the pixel electrode 106 as shown in FIG. 21. Referring to FIG. 22, the manufacturing method for this third conventional technique is explained.
On the glass substrate 100 was patterned a gate electrode 101 of a metal film, such as Cr or Al (see FIG. 22a), after which the gate insulating film 114 and the channel layer 102 formed of a-Si(I) and a contact layer 107 formed of a-Si(n+) are formed sequentially.
The semiconductor layer is then etched (see FIG. 22b) and a patterning step of removing the gate insulating film 114 of the contact area interconnecting the gate layer and the drain layer is then carried for forming a through-hole, not shown, for interconnecting the metal film forming the gate electrode 101 and the metal film forming the source electrode 104 and the drain bus line 112.
Then, similarly to the gate electrode 101, the drain electrode 103 formed by a metal layer, such as Cr or Al, source electrode 104 and the drain bus line 112 are formed, as shown in FIG. 22c. 
The passivation film 115 is then formed thereon and the through-hole 110 interconnecting the source electrode 104 and the pixel electrode 106 is provided (FIG. 22d). The pixel electrode 106 is then formed to provide a TFT array substrate (FIG. 22e).
In this structure, the storage capacitance electrode 108 is formed simultaneously with the gate electrode 101 by the patterning process forming the gate electrode 101. The number of the patterning steps is equal to that used in the first conventional technique.
Another conventional technique characterized in that occurrences of shorting between the drain bus line 112 and the pixel electrode 106 is reduced and the storage capacitance electrode serves simultaneously as the gate electrode (referred to as a xe2x80x98fourth conventional techniquexe2x80x99), as in the third conventional technique, is shown as a plan view in FIG. 23. FIG. 9 shows a cross-section taken along line D-Dxe2x80x2 in FIG. 23. The number of the patterning steps is equal to that used in the third conventional technique (see FIG. 22).
For explaining the effect of the third and fourth conventional techniques, FIG. 24 shows, in a plan view, the state of generation of a-Si residuals on a pixel. FIG. 25 shows a cross-sectional view taken along line I-Ixe2x80x2 in FIG. 24.
In the above-mentioned conventional technique, since the drain bus line 112 and the pixel electrode 106 are separated on the layer basis by the passivation film 115, no shorting occurs between the drain bus line 112 and the pixel electrode 106 even on occurrence of patterning defects in the course of the respective patterning steps. This reduces occurrences of point defects, that is bright and dark points.
However, even with this structure in which the drain bus line 112 and the pixel electrode 106 are separated form each other on the layer basis, electrically conductive foreign substances, such as a-Si, are left on occurrence of patterning defects, as shown in FIG. 26. Moreover, parasitic capacitances Ca between the drain bus line 112 contacted with the pixel electrode 106 and the pixel electrode 106 are increased. If there exist parasitic capacitances between the drain bus line 112 and the pixel electrode 106, the maintained voltage of the pixel Vp is modulated (xcex94Vp) as shown by the following equation
xe2x80x83(1):xcex94Vp=(Ca/Ct)xcex94VDxe2x80x83xe2x80x83(1)
where Ca: drain-to-pixel capacitance
Ct: total capacitance of the pixel
xcex94Vp: voltage modulation of a pixel
xcex94VD: drain amplitude
If the drain-to-pixel capacitance Ca is increased by the interposed electrically conductive foreign substances, the pixel voltage is lowered by 2xc3x97xcex94Vp as compared to that for regular pixels, so that point defects of semi-bright spots tend to be increased.
In the structure of the above-described third and fourth conventional techniques, in which, for suppressing shorting between the drain bus line and the pixel electrode, the drain bus line and the pixel electrode are separated on the layer basis by an insulating film, the residual a-Si, if produced as shown in FIGS. 24 and 25, leads to such an inconvenience that, since the residual a-Si is electrically connected to the drain bus line 112, the parasitic capacitance between the drain bus line 112 and the pixel electrode 106 is increased to increase point defects of semi-bright spots, that is points that have no optimum brightness.
It is therefore an object of the present invention to provide a transistor array in which occurrences of point defects of bright and dark spots ascribable to shorting between the drain bus line and the pixel electrode may be reduced.
It is a further object of the present invention to provide a transistor array in which a residual a-Si produced by patterning defects may be removed without increasing the number of patterning steps.
It is a still further object of the present invention to provide a transistor array in which the occurrences of point defects of bright and dark spots ascribable to increased parasitic capacitance between the drain bus line and the pixel electrode caused by electrical connection of residual a-Si to the drain bus line in order to reduce production loss and in order to improve yield and product quality.
Other objects of the present invention will become apparent in the entire disclosure.
According to one aspect of the present invention there is provided a thin-film transistor array comprising a matrix array of thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a contact layer, a drain electrode, a source electrode and a passivation film on a transparent glass substrate, and pixel electrodes disposed on the passivation film and which are electrically connected with the source electrode via an opening portion of the passivation film, and a storage capacitance electrode provided on the same layer as the gate electrode opposing each pixel electrode. The improvement resides in that an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the glass substrate, is formed only by the passivation film in at least a partial area.
The present invention provides a second aspect of thin-film transistor array comprising a matrix array of thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a contact layer, a drain electrode, a source electrode and a passivation film on a transparent glass substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source elect rode via an opening port ion in the passivation film, and a storage capacitance provided between each pixel electrode and the gate bus line of the previous stage. The improvement resides in that an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the glass substrate, is formed only by the passivation film in at least a partial area.
The present invention provides a third aspect of thin-film transistor array in which an insulating film for the pixel electrode is formed only by the passivation film in a slit area extending along the side of the pixel electrode.
The present invention provides a fourth aspect of thin-film transistor array comprising a matrix array of: thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a contact layer, a drain electrode, a source elect rode and a passivation film on a transparent glass substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source elect rode via an opening portion of the passivation film, and a storage capacitance electrode provided on the same layer as the gate electrode for opposing each pixel electrode. The improvement resides in that an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the glass substrate, is formed only by the gate insulating film in at least a partial area.
The present invention provides a fifth aspect of thin-film transistor array comprising a matrix array of thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a contact layer, a drain electrode, a source electrode and a passivation film on a transparent glass substrate; and pixel electrodes arranged on the passivation film and electrically connected with the source elect rode via an opening port ion in the passivation film, and a storage capacitance provided between each pixel electrode and the gate bus line of the previous stage. The improvement resides in that an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the glass substrate, is formed only by the gate insulating film in at least a partial area.
The present invention provides a sixth aspect of the thin-film transistor array according to the fourth and fifth aspects in which the insulating film for the pixel electrode is formed only by the gate insulating film in a slit area extending along the side of the pixel electrode.
Also, for accomplishing the above object, the present invention provides, as a seventh aspect, a first method for manufacturing a thin-film transistor array comprising: patterning a gate electrode and a storage capacitance electrode on a transparent glass substrate, sequentially forming a gate insulating film, a channel layer formed of an amorphous silicon of an intrinsic semiconductor and a contact layer of amorphous silicon of a n-type semiconductor. The method further comprises: patterning the amorphous silicon layer to the shape of an island, forming in the gate insulating film a through-hole serving for interconnecting a metal film forming the gate electrode and a metal film forming a drain electrode, a source electrode and a video signal line, and forming the drain electrode and the source electrode. The method further comprises: providing a passivation film and forming in the passivation film a through-hole for interconnecting the pixel electrode and the source electrode, and forming thereon the pixel electrode so as to interconnect to the source electrode.
In this method, the gate insulating film of at least a partial area of the insulating film for the pixel electrode, interposed between the pixel electrode of each pixel and the glass substrate and made up of the gate insulating film and the passivation film, is removed by the same patterning process as the patterning process used for forming the through-hole serving for interconnecting the metal film forming the gate electrode and the metal film forming the drain electrode, source electrode and the video signal line.
As a eight aspect, the present invention also provides a second method for manufacturing a thin-film transistor array comprising: patterning a gate electrode and a storage capacitance electrode on a transparent glass substrate, and sequentially forming a gate insulating film, a channel layer formed of an amorphous silicon of an intrinsic semiconductor and a contact layer of amorphous silicon of a n-type semiconductor. The method further comprises: patterning the amorphous silicon layer to the shape of an island, forming in the gate insulating film a through-hole serving for interconnecting a metal film forming the gate electrode and a metal film forming a drain electrode, a source electrode and a video signal line, and forming the drain electrode and the source electrode. The method further comprises providing a passivation film and forming in the passivation film a through-hole for interconnecting the pixel electrode, and the source electrode and forming thereon the pixel electrode so as to interconnect to the source electrode.
In this method, the passivation film of at least a partial area of the insulating film for the pixel electrode, interposed between the pixel electrode of each pixel and the glass substrate and which is made up of the gate insulating film and the passivation film, is removed by the same patterning process as the patterning process used for forming a through-hole adapted for interconnecting the pixel electrode and the source electrode.
According to the present invention, residual a-Si overlapped between the drain bus line or the gate bus line and the pixel electrode can be removed simultaneously by etching off the gate insulating film which is interposed between the transparent glass substrate and the pixel electrode, thus suppressing the reject ratio of point defects to improve the product yield. The gate insulating film has conventionally served as an insulating film for the pixel electrode.
According to further aspects of the present invention, the capacitive interconnection between the pixel electrodes and neighboring bus lines (e.g., gate bus lines and/or drain bus lines) by providing a boundary separating layer portion and/or slit portion which interrupts or breaks the capacitive coupling which might result from defective patterning, e.g., residual a-Si layer left at the boundary area between the pixel electrodes and neighboring bus lines. The slit portion may be filled with an insulating layer material, e.g., a passivation film or a gate insulating layer material.
In a ninth aspect there is provided a display device having gate bus lines, drain bus lines, and a thin-film transistor array disposed on a transparent substrate, the thin-film transistor array comprising a matrix array of: thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a drain electrode, a source electrode and a passivation film on the substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source electrode, with a storage capacitance elect rode being provided the substrate opposing each pixel electrode, wherein an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the substrate, is formed only by the passivation film in at least a partial area neighboring the gate bus lines and/or drain bus lines.
In a tenth aspect, there is provided a display device having gate bus lines, drain bus lines and a thin-film transistor array disposed on a transparent substrate, the thin-film transistor array comprising a matrix array of: thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a drain electrode, a source electrode and a passivation film on the substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source electrode, with a storage capacitance being provided between each pixel electrode and the gate bus line of the previous stage, wherein an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the glass substrate, is formed only by the passivation film in at least a partial area neighboring the gate bus lines and/or drain bus lines.
In an eleventh aspect, there is provided a display device having gate bus lines, drain bus lines and a thin-film transistor array disposed on a transparent substrate, the thin-film transistor array comprising a matrix array of: thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a contact layer, a drain electrode, a source electrode and a passivation film on a transparent substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source electrode via an opening portion of the passivation film, with a storage capacitance elect rode being provided on the same layer as the gate electrode opposing each pixel electrode, wherein an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the substrate, is formed only by the gate insulating film in at least a partial area neighboring the gate bus lines and/or drain bus lines.
In a twelfth aspect, there is provided a display device having gate bus lines, drain bus lines and a thin-film transistor array disposed on a transparent substrate, the thin-film transistor array comprising a matrix array of: thin-film transistors, each made up of a gate electrode, a gate insulating film, a channel layer, a drain electrode, a source electrode and a passivation film on the substrate, and pixel electrodes disposed on the passivation film and electrically connected with the source electrode, with a storage capacitance being provided between each pixel electrode and the gate bus line of the previous stage, wherein an insulating film for the pixel electrode, comprised of the gate insulating film and the passivation film and interposed between the pixel electrode of each pixel and the substrate, is formed only by the gate insulating film in at least a partial area neighboring the gate bus lines and/or drain bus lines.